The present invention relates to a D/A converter wherein resistor strings are mounted on a semiconductor substrate.
FIG. 3 is a circuit diagram showing an example configuration for a conventional D/A converter of a resistor string type. The D/A converter receives data to be converted (hereinafter referred to “conversion data”) as a digital signal of six bits, converts this digital signal into an analog signal, and outputs the analog signal. In FIG. 3, reference numerals 1 and 2 denote 3-bit decoders, respectively.
The 0-th bit D0 (LSB) to the second bit D2 of the conversion data are input to the input end of the decoder 1 through exclusive OR circuits 3 to 5, while the third bit D3 to the fifth bit D5 (MSB) of the conversion data are input to the input end of the decoder 2.
Voltage selection circuits 11 to 18 have the same structure, i.e., each includes a resistor string, which is formed by connecting nine resistors in series, and nine FETs (Field-Effect Transistors). In each of the voltage selection circuits 11 to 18 of the nine resistors constituting the resistor string, the uppermost resistor (the resistor at the top in FIG. 3) and the lowermost resistor (the resistor at the bottom in FIG. 3) have a resistance of R/2, while the other resistors have a resistance of R. The sources of the eight FETs are connected to the individual junction points of the resistors, and the drains of the FETs are connected in common to the source of the ninth FET.
The gates of the lowermost FETs of the voltage selection circuits 11 to 18 are connected to an output end 0 of the decoder 1, the gates of the second lowest FETs are connected to an output end 1 of the decoder 1, . . . , and the gates of the eighth lowest FETs are connected to an output end 7 of the decoder 1. The gates of the uppermost FETs of the voltage selection circuits 11 to 18 are respectively connected to output ends 0 to 7 of the decoder 2, and the drains of these FETs are connected to an output terminal OUT. A low voltage VR (−) is applied to an end P0 of the lowermost resistor of the voltage selection circuit 11, and a high voltage VR (+) is applied to an end P8 of the lowermost resistor of the voltage selection circuit 18. Between the end P0 of the voltage selection circuit 11, to which the low voltage VR (−) is applied, and the end P8 of the voltage selection circuit 18, to which the high voltage VR (+) is applied, the resistor strings of the voltage selection circuits 11 to 18 are connected through junction points P1, P2, P3, P4, P5, P6 and P7, while being doubled back in a ladder shape.
With this configuration, based on the 0-th bit D0 to the second bit D2 of the conversion data, the decoder 1 turns on one of the FETs provided for each of the resistor strings of the voltage selection circuits 11 to 18. For example, when the value of the 0-th bit D0 to the second bit D2 of the conversion data is represented by “010” (2), the third lowest FETs of the individual resistor strings are caused to be on. Further, the decoder 2 selectively turns on the uppermost FET of one of the voltage selection circuits 11 to 18. For example, when the value of the third bit D3 to the fifth bit D5 of the input conversion data is represented by “100” (4), the uppermost FET of the voltage selection circuit 15 is turned on. Therefore, in this example, when conversion data (digital data) is “100010”, a voltage-dividing-point voltage at the junction point for the third and fourth lowest resistors of the resistor string of the voltage selection circuit 15 is output to the output terminal OUT as a voltage to be transformed.
When this D/A converter is mounted on a semiconductor substrate by using a semiconductor integrated circuit, multiple resistors are connected in series, and a divided voltage is selected and output. Therefore, it is desirable that there be no errors in the resistance values for the resistors constituting the resistor strings. However, in actuality, since because of the manufacturing process the sheet resistance distribution is not linear, the occurrence of errors in the resistances can not be avoided. Usually, in accordance with the locations of the resistors on the semiconductor substrate, an error occurs in that the resistances are varied with a specific gradient (monotonously increased or decreased). Especially, the column direction of the resistor strings is affected by this gradient. Therefore, as in the example shown in FIG. 3, assuming that the total resistance for the resistor string of the voltage selection circuit 11 is 8R, the total resistance for the resistor string of the voltage selection circuit 12 is 8R+Δ, the total resistance for the resistor string of the voltage selection circuit 13 is 8R+2Δ, . . . , and the total resistance for the resistor string of the voltage selection circuit 18 is 8R+7Δ. In this case, the total resistance for all the resistor strings is 64R+28Δ, and the average resistance for one resistor string is 8R+3.5Δ.
Therefore, assuming that the junction point of the voltage selection circuits 11 and 12, the junction point of the voltage selection circuits 12 and 13, . . . and the junction point of the voltage selection circuits 17 and 18 correspond to P1, P2, . . . and P7, it is preferable that, the resistances at the junction points P1, P2, . . . and P7 with respect to the point P0 represent “ideal values” as indicated in FIG. 4. However, the actual resistances at the junction points P1 to P7 are “resistance addition values”, as indicated in FIG. 4. When the “ideal values” are subtracted from the “resistance addition values” in FIG. 4, the “differences” shown in FIG. 4 are obtained and are represented graphically as shown in FIG. 4. As is apparent from the graph in FIG. 4 for the D/A converter in FIG. 3, influences due to resistance errors having specific gradients (monotonous increases or decreases) are accumulated, the linearity (the linear accuracy of the output) has a characteristic represented by a convex shape (or a concave shape), and the linearity error becomes largest near the center of the graph.
In order to resolve this linearity error of the D/A converter due to the resistance error, techniques disclosed in patent documents 1 to 3 are well known. According to the techniques described in these documents, two types of resistor groups are arranged in opposite directions to offset the distribution of resistance errors. However, these techniques require twice as many resistors as are conventionally employed, and when a D/A converter is prepared by using a semiconductor integrated circuit, the dimensions of the circuit are twice as large.
According to a technique disclosed in patent document 4, the rows and the columns of resistors arranged in a matrix are divided by two to provide four resistor groups, and to offset the resistance errors, these resistor groups are connected in the shape of a cross. However, while for this circuit linearity errors are theoretically reduced to zero near the center, no other error offset effect can be obtained.
Patent Document 1
JP-A-11-145835
Patent Document 2
Japanese Patent No. 2864877
Patent Document 3
JP-A-61-26330
Patent Document 4
Japanese Patent No. 2737927